Minimizing path delay in a machine by compensation of timing through selective placement and partitioning
US5237514A · kind A · utility
112Cited by
11References
22Claims
0Family size
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Key dates
| Filing date | Dec 21, 1990 |
| Grant date | Aug 17, 1993 |
| Priority date | — |
| Expiry date | Dec 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for minimizing cycle time to improve machine performance is described. The approach prioritizes placement and partitioning decisions based on the criticality of paths and their constituent net segments. It provides an initial coarse approximation to a final more optimum configuration by iteratively improving on it through the use of deterministic techniques. The method optimizes placement by means of heuristic algorithms that are based on a cost function that is dependent on net segment and path criticality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.