Processor communication bus
US5237567A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1990 |
| Grant date | Aug 17, 1993 |
| Priority date | — |
| Expiry date | Oct 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/374
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system that contains plural computer resource elements, such as multiple processor and memory units, with those elements communicating digital information over a common communications bus, high communications bus efficiency is achieved. An interface permits each of said processor and memory elements to individually and independently access either the data bus, without busying the address bus, or the address bus without busying the data bus, with bus access being limited to a fixed interval of time. Different ones of said processor and memory units may thus simultaneously transfer digital information over the respective address and data bus. The foregoing system includes a bus contention and priority protocol to eliminate the possibility of data collision and includes identification lines for identifying each processor element accessing the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.