Large scale integrated circuit configured to eliminate clock signal skew effects
US5239215A · kind A · utility
38Cited by
5References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 20, 1992 |
| Grant date | Aug 24, 1993 |
| Priority date | — |
| Expiry date | Nov 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15066
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has a clock signal supply circuit positioned in a central region of the IC chip, for supplying a clock signal to each of a plurality of outer regions of the integrated circuit disposed around the central region, for thereby substantially eliminating clock signal skew effects. The clock signal may be distributed directly to circuit elements within the respective outer regions, or transferred to these circuit elements via respective buffer circuits which are formed at the centers of these regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.