Control circuit having outputs with differing rise and fall times
US5239237A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1992 |
| Grant date | Aug 24, 1993 |
| Priority date | — |
| Expiry date | Oct 8, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM. When a control signal is used in a buffer comprising a pull up and a pull down transistor, the input signal to the buffer is applied to the gate of the transistors ind the control circuit. The two control signals are applied to the gates of the pull up and p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.