Semiconductor memory device with readout data buses connecting local and main sense amplifiers
US5239507A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1991 |
| Grant date | Aug 24, 1993 |
| Priority date | — |
| Expiry date | Feb 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Readout data amplified by each local sense amplifier is provided to the corresponding readout data bus. Each readout data bus is connected to a plurality of main sense amplifiers (for example, a main sense amplifier for x1 and a main sense amplifier for x2). Each main sense amplifier includes a clamp transistor for clamping the potential of the readout data bus always to a constant potential, whereby increase in speed of readout data is performed by the clamp transistor. The base potential of the clamp transistor in each main sense amplifier is controlled in response to a switching control signal. As a result, a plurality of main sense amplifiers connected to one readout data bus are switched selectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.