Method for characterizing failed circuits on semiconductor wafers
US5240866A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1992 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Feb 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Failed circuits (e.g., defects) on each of a plurality of semiconductor wafers (10) in a batch can be characterized for the purpose of identifying defect sources by first mapping the defective ones of the circuits (12.sub.1 -12.sub.n) in each wafer. A determination is made to see if the defects in the defect pattern map associated with each wafer (10) are sufficiently clustered to warrant further study. The defect pattern maps for the wafers in the batch identified as having spatial clustering present are smoothed and thresholded to identify where spatial clusters occur. All such smoothed and thresholded defect pattern maps are separated into groups in accordance with the pattern of defects. The pattern of defects associated with each group is then analyzed to determine if any relationship exists between the pattern and the order of the process steps or one of the patterns in a library of patterns associated with particular failure modes. Should a match be found, then the particular process step(s) or failure mode(s) responsible for such defects can be indicted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.