Semiconductor memory device
US5241205A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1992 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Sep 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
A semiconductor memory device is provided which includes a plurality of memory cells, each of which includes: an active region having an MOS transistor formed in the surface portion of a semiconductor substrate; a gate electrode formed on the substrate for the MOS transistor so as to divide the active region into a source-side active region with a storage contact and a drain-side active region with a bit contact, the portion of the active region which is positioned under the gate electrode functioning as a channel region for the MOS transistor; a first impurity-implanted region formed in a portion of the source-side active region so as to overlap with part of the storage contact and the gate electrode, the portion of the source-side active region which overlaps with the first impurity-implanted region functioning as a source region for the MOS transistor; and a second impurity-implanted region formed in a portion of the drain-side active region so as to overlap with at least one part of the bit contact and the gate electrode, the portion of the drain-side active region which overlaps with the second impurity-implanted region functioning as a drain region for the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.