Dram interface adapter circuit
US5241222A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1991 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Dec 20, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is an interface adapter circuit that allows multiple types of 256K by 16 bit dynamic random random access memories to be used by system manufacturers. The interface adapter circuit selects a type of outputs signal set to produce responsive to a mode selection signal. The circuit converts an input signal set including a column address probe and low and high by write signals into either a first output signal set, including one column address strobe and high and low byte write signals, or a second output signal set including a single write signal and high and low column address signals, responsive to the selection signal. The circuit includes a logic circuit for producing the signals and flip flops for holding the signal produced. The flip flops also synchronize other memory address, etc. signals with the signals produced by the adapter circuit. The interface adapter circuit can also convert write nd column address timing signals and low and high byte write signals into the two sets responsive to a selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.