NOR.sub.i circuit/bias generator combination compatible with CSEF circuits
US5241223A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1992 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | May 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
NOR logic performed by a half current switch emitter follower ("HCSEF") circuit utilizing a transistor operated in the inverse active mode as its current source and having logic levels compatible with those of current switch emitter follower ("CSEF") circuitry is combined with a novel reference bias generator that controls the logic low voltage level by controlling the voltage drop across the current source. The NOR.sub.i circuit utilizes less power than CSEF circuits, has a natural threshold equal to the threshold of CSEF circuits to which it is coupled, has a delay skew of approximately 1:1, and maintains minimum signal levels with respect to variations on V.sub.cc. The reference bias generator compensates for temperature, process variables and variations in the NOR.sub.i circuit and in the power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.