Phase locked loop reference slaving circuit
US5241285A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 1991 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Oct 3, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit may be utilized as a low jitter clock regenerator in order to generate an extremely stable low jitter signal which is to a large extent immune from input phase and frequency noise. The slaving clock generates an output at a fixed phase relationship to a reference input. The clock regenerator is advantageously implemented by a logic gate type phase detector connected to a multi-stage loop filter. The loop filter output is connected to a phase correction circuit whose output is mixed with the loop filter output to provide a control input to a voltage controlled oscillator. The voltage controlled oscillator output may be provided directly, or through a frequency divider, to a feed-back input of the phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.