Biasing scheme for improving latitudes in the tri-level xerographic process
US5241358A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1991 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Oct 7, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03G15/0121
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The operating latitude of the tri-level xerographic process is improved by replacing the standard DC bias that is applied to one or both of the developer housings in conventional tri-level imaging with a chopped DC (CDC) developer bias. Chopped DC biasing is the alternate application of two discrete bias voltages to a developer strucrute in a periodic fashion at a given frequency, with the period of each cycle divided up between the two bias levels at a duty cycle of from 5-10% or 90-95% depending upon which of the two developer structures is being biased. In the case of the DAD developer structure the duty cycle of higher of the two biases is 5-10% and in the case of a CAD developer structure the duty cycle of higher of the two biases is 90-95%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.