Burst time division multiplex interface for integrated data link controller
US5241541A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1990 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Mar 15, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable and to be able to devote maximum processing time …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.