Automatic processor module determination for multiprocessor systems for determining a value indicating the number of processors
US5241627A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1989 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | May 30, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus controller, operable to grant access to a bus structure for communication between a number of individual processor modules interconnected by the bus to form a multiprocessor system, is also operable to determine the number of processors connected to the bus. The bus controller, in round-robin fashion, sequentially grants each processor access to the bus by commanding the processor to send data. The processor responds either by sending data in synchronism with a data clock supplied by the bus controller or, if no data is to be sent, responds with a no acknowledgment (NAK) signal. Initially, and periodically, the bus controller checks to determine the number of processors by, beginning with the highest identifying numbered processor, sending to that processor a send command, and looking for a response either in the form of data being sent or a NAK signal. If neither of these responses is received, the bus controller will transmit a send command to the next highest identifying numbered processor in order, continuing this process until a response is received. At that time, the identifying number of the processor is saved, and thereafter only that number of processors are in the b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.