Dual cache memory
US5241638A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1985 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Aug 12, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual cache memory system employs a search cache addressed by virtual addresses, the search cache containing a plurality of recently used, pre-translated physical addresses. A map cache contains virtual address bound data and relocation data to map the virtual address space to physical address space. Upon receipt of a virtual address, a search of the search cache is first conducted to retrieve the associated physical address if it has been already translated. If not, a binary search of the memory map using the map cache is conducted to find that map entry whose virtual address bound identifies the region of virtual addresses containing the virtual address being mapped. The physical address is constructed from the retrieved relocation data and virtual address, and is written into the search cache for future use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.