Data processor for executing data saving and restoration register and data saving stack with corresponding stack storage for each register
US5241679A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1990 |
| Grant date | Aug 31, 1993 |
| Priority date | — |
| Expiry date | Jun 27, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor comprises a plurality of registers 1 (registers a to d), a plurality of data saving stack memory devices 2 coupled to the registers 1 for exclusive use thereof, respectively, and an instruction decoder for decoding instructions for controlling the registers 1 and the data saving stack memory devices 2 in accordance with the result of the instruction decoding. In response to an instruction "PUSH", the contents of the registers 1 (registers a to d) are selectively saved to the data saving stack memory device 2. In response to a instruction "POP", the contents of the data saving stack memory devices 2 are selectively restored to the registers 1 (registers a to d). Each of the instructions "PUSH" and "POP" has a field for indicating need or needlessness of the saving and restoration for each of the registers 1 and each of the data saving memories 2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.