Logic circuit using vertically stacked heterojunction field effect transistors

US5243206A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• X. Theodore Zhu · Chandler, US
• Jonathan K. Abrokwah · Tempe, US
• Herbert Goronkin · Tempe, US
• William J. Ooms · Chandler, US
• Carl L. Shurboff · Grayslake, US

Key dates

• Filing date: Jul 2, 1991
• Grant date: Sep 7, 1993
• Expiry date: Jul 2, 2011

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/903

Abstract

Logic circuits using a heterojunction field effect transistor structure having vertically stacked complementary devices is provided. A P-channel quantum well and an N-channel quantum well are formed near each other under a single gate electrode and separated from each other by a thin layer of barrier material. P-source and P-drain regions couple to the P-channel. N-source and N-drain regions couple to the N-channel. The P-source/drain regions are electrically isolated from the N-source/drain regions so the P-channel and N-channel devices may be interconnected to provide many logic functions.