Fine/coarse wired-or tapped delay line
US5243227A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1991 |
| Grant date | Sep 7, 1993 |
| Priority date | — |
| Expiry date | Nov 1, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a delay line for providing fine timing adjustment on subsequent edges of an input signal. The delay line comprises a plurality of delay elements for fine tuning the position in time of the timing edges of the input signal. Each delay element has a data input and data output where the data output is connected to the subsequent delay element's data input, thereby forming a delay line with delay elements connected in series. This implementation facilitates the addition of fine increments of delay to be added to the input signal and thereby enable fine tuning of timing edges. Also, included is a wired-OR multiplexor having data inputs connected to the data outputs of the plurality of the delay elements and a control input to select a particular data output to thereby provide an output signal having delayed timing edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.