Noninverting Bi-CMOS gates with propagation delays of a single Bi-CMOS inverter
US5243237A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1992 |
| Grant date | Sep 7, 1993 |
| Priority date | — |
| Expiry date | Jan 22, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a noninverting Bi-CMOS gate, one or more passgates are utilized in the control path leading to a bipolar output transistor which switches the output of the Bi-CMOS gate. The control gate of one of the MOS transistors of a passgate is connected to an input signal of the Bi-CMOS gate. The control gate of the other MOS transistor is connected to the complement of the input signal. The output of the passgate is connected to the base of the bipolar output transistor. More than one such passgate connected to an input signal and its complement can be used. If multiple passgates are used, the outputs of the passgates may be tied together. This technique, utilizing the switching of the passgates with the input signals and their complements, is employed to create a family of Bi-CMOS noninverting gates such as buffers and AND gates. The propagation delay through the noninverting Bi-CMOS gates of the present invention are roughly equal to the propagation delay of a single Bi-CMOS inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.