Comparison and verification system for logic circuits and method thereof
US5243538A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1990 |
| Grant date | Sep 7, 1993 |
| Priority date | — |
| Expiry date | Aug 7, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a hierarchy design is attempted in a logic design of a logic circuit, a system for verifying an equivalence between an upper level logic and a lower level logic is required. When the two different level logics are compared, the logics are once converted to Boolean expressions regardless of logic expressions of the logics, involving a logic circuit diagram and a truth table, and Shannon's formula is applied to the two Boolean expressions under a same order of variables to be extracted, to thereby produce binary decision diagrams (BDDs). When the equivalence between the produced BDDs is determined, the BDDs are simplified, respectively, and the simplified BDDs are integrated from the branches, and a determination can be carried out one time, i.e, without a repeat process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.