Semiconductor memory device
US5243559A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1991 |
| Grant date | Sep 7, 1993 |
| Priority date | — |
| Expiry date | Dec 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a semiconductor substrate of a first conduction type, a memory cell having a floating gate and a control gate which are formed on a main surface of the semiconductor substrate and stacked with an interlayer insulating film interposed therebetween and having a three-layer structure of an oxide film, a nitride film and another oxide film, a decoder for supplying a voltage to the memory cell, a first well formed on the substrate surface and having a second conduction type different from the first conduction type, and a second well formed in the first well and having the first conduction type, wherein one of the memory cell and the decoder is formed in the second well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.