Deselect circuit
US5243572A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1992 |
| Grant date | Sep 7, 1993 |
| Priority date | — |
| Expiry date | Jan 15, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A deselect circuit (10) receiving a variable number of input signals which enables an output stage to generate a logic state signifying a deselect condition at a deselect output (12). The deselect circuit (10) operates synchronously having a clock signal (21) and inverted clock signal (22) to control internal timings. The deselect output (12) is preset to a logic state signifying a select condition prior to starting a deselect sequence, thus eliminating the need for circuitry to generate the select condition. The path for generating a deselect condition comprises a transmission gate which couples the inverted clock signal to a driver stage, a multiple input switch which couples the driver stage to a output stage, and the output stage which generates a logic state signifying a deselect condition at the deselect output (12). A sensing circuit is used to sense the select condition and enable a second driver stage to maintain the select condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.