Apparatus and method for assuring stable clock generator during oscillator start-up
US5243637A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1992 |
| Grant date | Sep 7, 1993 |
| Priority date | — |
| Expiry date | Jun 4, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold. The pulse generator module (20) functions as a modified edge-triggered D flip-flop (21, 23) that triggers in response to paired transitions of CLOCK A and CLOCK B (indicating that the oscillator clock has cycled through both the high and low amplitude thresho…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.