Input/output system for parallel processing arrays
US5243699A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1991 |
| Grant date | Sep 7, 1993 |
| Priority date | — |
| Expiry date | Dec 6, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17393
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.