Floating gate non-volatile memory blocks and select transistors
US5245570A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1990 |
| Grant date | Sep 14, 1993 |
| Priority date | — |
| Expiry date | Dec 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device is described. The memory device includes a global bit line, a first block, and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate and a control gate. A first word line is coupled to the control gate of the first memory cell. A first local bit line is coupled to the drain region of the first memory cell. A first selecting means couples the first local bit line to the global bit line. The second block includes a second memory cell having a drain region, a source region, a floating gate and a control gate. A second word line is coupled to the control gate of the second memory cell. A second local bit line is coupled to the drain region of the second memory cell. A second selecting means couples the second local bit line to the global bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.