Floating gate nonvolatile memory with reading while writing capability
US5245572A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1991 |
| Grant date | Sep 14, 1993 |
| Priority date | — |
| Expiry date | Jul 30, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate nonvolatile memory. The memory includes a first memory array and a second memory array. A first address register is provided for storing a first address for the first memory array. A second address register is provided for storing a second address for the second memory array. A multiplexer is coupled to the first memory array and the second memory array at one end and an output of the memory device at the other end for selectively coupling one of the first memory array and the second memory array to the output at a time. Array select circuitry responsive to an incoming address is provided for selecting the first memory array for a reprogramming operation and the second memory array for a read operation. The array select circuitry directs the first address to the first address register and the second address to the second address register. The array select circuitry controls the multiplexer for coupling the second memory array to the output during the reprogramming operation of the first memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.