Random access memory with page addressing mode
US5245585A · kind A · utility
Inventors
Key dates
| Filing date | Oct 22, 1990 |
| Grant date | Sep 14, 1993 |
| Priority date | — |
| Expiry date | Oct 22, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.