High-speed determining unit for prioritizing and arbitrating among competing input signals
US5245603A · kind A · utility
20Cited by
12References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 10, 1991 |
| Grant date | Sep 14, 1993 |
| Priority date | — |
| Expiry date | Jun 10, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5679
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A determining unit in a computer, communication of other system for determining which one of a plurality of requests by competing input signals is to be honored. The determining unit includes a priority and an arbiter unit with a plurality of stages of arbiter blocks cascaded together from arbiter blocks in a first stage to arbiter blocks in a last stage in a binary tree. The forward output signals from blocks in one stage connect as forward input signals to blocks in a next stage and reverse output signals from blocks in one stage connect as reverse input signals to blocks in a previous stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.