Data processing system with multiple communication buses and protocols
US5245703A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 1989 |
| Grant date | Sep 14, 1993 |
| Priority date | — |
| Expiry date | Jun 21, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system is presented, comprising at least one central unit (CPU), at least one central memory (MMU), and internal communication bus to which the CPU and MMU are connected, at least one peripheral unit, a control module (IOM), and an external communication bus to which the peripheral unit and the control module are connected. In this system, the IOM is also connected to the internal communication bus. The internal and external communication buses are of differing types. Within the IOM, the connection to the internal communication bus is via an internal interface device (CLM), while the connection to the external communication bus is via an external interface device (PLM). An inter-device interface (PLI), also within the IOM, connects the CLM and PLM, so as to adapt the protocols of each to the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.