Method of connecting a spaced IC chip to a conductor and the article thereby obtained
US5245750A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 1992 |
| Grant date | Sep 21, 1993 |
| Priority date | — |
| Expiry date | Feb 28, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip (26, 34) is connected to a circuit trace by providing a raised feature on a circuit trace (17, 28) which is coated with a material capable of forming an electrical connection (23, 32), as well as an attachment when the pad (25, 33) of an integrated circuit chip (26, 34) is brought into engagement with it. This material may be solder (23) or it may be a Z-axis adhesive (32) which becomes conductive at areas where it is compressed. The raised feature or bump (18, 31) on the circuit trace (17, 28) may be produced by providing a mandrel (10) having a recess (12) complementary to the raised feature (18, 31) to be provided, and suitably plating the circuit trace (17, 28) on the mandrel (10) including the recessed area (12). Upon subsequent lamination of a dielectric layer (19, 30) and removal from the mandrel (10), there is produced a circuit trace (17, 28) on a dielectric with a raised feature (18, 31) which can be used to attach to an integrated circuit chip (26, 34).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.