Method and apparatus for testing a digital system for the occurrence of errors
US5247458A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 11, 1990 |
| Grant date | Sep 21, 1993 |
| Priority date | — |
| Expiry date | Sep 11, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for testing a digital signal processing system for the occurrence of bit errors. A mathematically-predictable test signal is applied to the input of a digital signal processing system The test signal components are removed from the output signal of the system by filtering, curve fitting or other techniques, leaving a resultant signal. The peak amplitude of the resultant signal is measured as an indication of the occurrence of errors. A time integrated measure of the resultant signal is made as an indication of the amount of noise and distortion artifacts. The peak amplitude is compared to a reference or the time integrated measure to identify errors. A histogram of the resultant signal amplitude may also be produced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.