Code error correction apparatus
US5247523A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1990 |
| Grant date | Sep 21, 1993 |
| Priority date | — |
| Expiry date | Jul 11, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2927
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A product code block generated by adding an outer code block and an inner code block to digital information signal arranged in matrix is received at least twice by a code error correction apparatus. In decoding the first received product code block by use of an inner code parity, an error flag is set for an inner code block having an uncorrectable error by an inner code parity. In decoding the second received product code block by use of an inner code parity, the error flag is referrenced so that an inner code block that could be correctly decoded or corrected in the second decoding of all the inner code blocks having an uncorrectable error in the first decoding is replaced by the second inner code block. Also, the check information such as a check sum is generated and stored each time of receiving, and an error flag is set for even an inner code block that could be corrected in either the first or second decoding, if the check sums for them fail to coincide with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.