Structure for improving gate oxide integrity for a semiconductor formed by a recessed sealed sidewall field oxidation process
US5248350A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1990 |
| Grant date | Sep 28, 1993 |
| Priority date | — |
| Expiry date | Nov 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming field oxide regions between active regions in a semiconductor substrate. Pad oxide, polysilicon and first silicon nitride layers are successively formed over substrate active regions. The first nitride layer, polysilicon layer, pad oxide layer and a portion of the substrate are then selectively etched to define field oxide regions with substantially vertical sidewalls. A second silicon nitride is provided on the substantially vertical sidewalls, and field oxide is grown in the field oxide regions. The first silicon nitride, polysilicon and pad oxide layers are then removed. The presence of the polysilicon layer prevents the formation of a sharp corner between the field oxide and active regions if an overetch occurs during the removal of the pad oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.