Method for the hierarchical comparison of schematics and layouts of electronic components
US5249133A · kind A · utility
60Cited by
5References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 10, 1991 |
| Grant date | Sep 28, 1993 |
| Priority date | — |
| Expiry date | Apr 10, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention takes advantage of the hierarchical nature of the design to perform a hierarchical comparison on as many blocks and sub-blocks which can be matched between the layout and the logic design. Because the internal connections were previously verified when the first occurrence of the block was compared, repetition of lengthy comparisons of multiple occurrences of the same blocks in the designs is avoided and subsequent comparisons are performed simply by comparing the input and output connections to the block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.