Buffer memory data flow controller
US5249271A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1993 |
| Grant date | Sep 28, 1993 |
| Priority date | — |
| Expiry date | Feb 19, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data flow control system for regulating the flow of data through a buffer memory in a data storage system controller. The data flow controller system includes an up-down counter that is decremented for every byte of data that is placed into the controller's buffer memory, and incremented for every byte of data that is taken out of the buffer memory. The counter is preset to an initial value that represents the minimum amount of data that must be in the buffer memory before that data can be released to the storage system or to the computer interface, thereby permitting validation of the data prior to release. The value of the counter represents the amount of data that is in the buffer memory less the initial offset value. Detector circuitry coupled to the counter enables or disables the storage system or the computer interface depending upon the validity of the data in the buffer memory and the operational status of the storage system and the computer interface. An additional feature of the invention permits using the buffer memory as a cache for data read from the storage system. Intermediate status information about the buffer memory is generated in order to permit the storage s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.