Selectively locking memory locations within a microprocessor's on-chip cache
US5249286A · kind A · utility
52Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1992 |
| Grant date | Sep 28, 1993 |
| Priority date | — |
| Expiry date | Nov 24, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.