Processing communication system having a plurality of memories and processors coupled through at least one feedback shift register provided from ring configured input stations
US5249301A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1993 |
| Grant date | Sep 28, 1993 |
| Priority date | — |
| Expiry date | Feb 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is in the realm of an information processing system including a central unit which includes several processors sending requests to several processors sending requests to several memories via an input interconnection and receiving responses from those memories via an output interconnection. To simplify the input interconnection when the number of processors and memories increases, a ring of stations equipped with a register is used. A request given by a processor is loaded into a station when that station is free or becomes free, If not the ring functions a fed back shift register. A station becomes free when the request contained in the station downstream is accepted by a memory. An analogous device can be used for the output interconnection. A notable application is vector processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.