Method of fabricating a miniaturized heterojunction bipolar transistor
US5250448A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1991 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Jan 31, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/821
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heterojunction bipolar transistor of this invention is a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer. A method of fabricating the transistor includes the steps of forming a first semiconductor layer of a first conductivity type on a substrate, which first semiconductor layer serves as a collector layer, etching an unnecessary portion of the first semiconductor layer to form a groove, and burying an insulating layer in the groove, forming a second semiconductor layer serving as a base layer on the first semiconductor layer and that part of the insulating layer surrounding the first semiconductor layer, and forming a third semiconductor layer of the first conductivity type, serving as an emitter layer, on the second semiconductor layer. According to the method of this invention, a groove is formed, in advance, in an unnecessary part of the first semiconductor layer, which becomes the collector layer, and the insulating layer is buried in the groove. Thus, a flattened wafer having an element region defined therein can be obta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.