Dynamic logic circuit with reduced operating current
US5250857A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 27, 1992 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Jan 27, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a dynamic logic circuit, an X decoder and a Y decoder receive a more significant bit portion and a less significant bit portion of an internal address generated by a sequencer, respectively. A precharge signal supplied to the X decoder is generated when the sequencer start signal is applied to the sequencer, or when the more significant bit portion of the address supplied to the X decoder changes or is incremented. Therefore, even when the less significant bit portion of the address supplied to the Y decoder changes or is incremented, the precharge signal supplied to the X decoder is not generated if the more significant bit portion of the address supplied to the X decoder does not change. Thus, the number of the precharge/discharge is reduced, and accordingly, the operating current of the dynamic logic circuit is decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.