Waveform peak capture circuit for digital engine analyzer
US5250935A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1990 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Sep 24, 2010 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02P17/08
- WIPO fieldEngines, pumps, turbines
- WIPO sectorMechanical engineering
Abstract
A digital engine analyzer has an oscilloscope display and is controlled by microprocessors operating under menudriven stored program control. The analyzer receives analog input signals from an engine being analyzed. Peak capture circuitry permits the display of a full cylinder period of a waveform, even though it contains very high frequency portions, by selectively switching between normal and high resolution modes. The circuitry samples the analog waveform at a very high rate and selects samples for display at a much slower display rate. The circuitry captures and stores the highest magnitude sample in each cylinder cycle by storing each sample only if its magnitude exceeds that of the previously stored sample. In the normal mode, at each display clock pulse the most recent sample is selected for display, irrespective of its magnitude. In the high resolution mode the stored peak value is selected for display at each display clock pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.