Multiple transistor clamping device and method
US5251098A · kind A · utility
16Cited by
4References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 31, 1992 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Jan 31, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heat sink-hybrid circuit assembly clamping device (100) and method (200) are provided for minimizing hybrid circuit assembly substrate-transistor solder joint stress. The clamping device is positioned and selected to provide a net coefficient of linear expansion (CLE) substantially of a magnitude equal to a net coefficient of the substrate material such that uniform pressure and contact are obtained between the transistors of hybrid circuit assemblies and the heat sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.