Method and apparatus for processing sign-extension bits generated by modified booth algorithm
US5251167A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1991 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Nov 15, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49994
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for adding signed partial products without generating sign extension subfields is disclosed. The method and apparatus are particularly useful when employed in conjunction with multiplication algorithms such as the 3-bit modified Booth algorithm and the like. Rather than adding a sign extension subfield to extend the left side of each partial product row into alignment with the leftmost bit position of the sum field (e.g., the full product field), a special sign-extension "correction" factor is added to the nonextended partial products. The correction factor mimics the effect of summing the sign-extension bits which would conventionally have been added to the partial product rows. The special correction factor contains fewer bits than the total number of bits contained in all the eliminated sign extension portions, and accordingly, less computer circuitry and/or computer time is required for performing the partial product summation operation. A method which minimizes the computer circuitry or time needed for generating the correction factor is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.