Digital signal processor synchronous network

US5251208A · kind A · utility

Assignee

• AT&T Bell Laboratories · US

Inventors

• Ronald J. Canniff · Naperville, US
• Philip Chao · Naperville, US
• Alan H. Matten · Chicago, US
• Charles E. Stroud · Lexington, US

Key dates

• Filing date: Dec 19, 1991
• Grant date: Oct 5, 1993
• Expiry date: Dec 19, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L12/52
• WIPO field: Control
• WIPO sector: Instruments

Abstract

An arrangement where a plurality of digital signal processors cooperate in the performance of a digital signal processing function. The processors are interconnected by means of a synchronous network which provides time division multiplexed communication links between processors for communicating intermediate processing results therebetween. The synchronous network includes a plurality of port circuits each associated with one of the processors. The network generates timing signals defining frames of time slots and defining superframes comprising N frames. Each port circuit can control the transmission of digital data from a memory of its associated processor during M1 time slots of each superframe. Each port circuit can also control the writing of digital data to its associated processor during M2 time slots of each superframe. The value of N, the number of frames per superframe, is programmable. The values of M1 and M2 are also programmable for each port circuit.