Synchronizing method for SDH systems as well as method of and circuit arrangement for identifying different data structures
US5251239A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1991 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Apr 22, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/048
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for synchronizing a system frame-structured in accordance with a digital synchronous hierarchy, particularly as specified in CCITT G.708. In a hunt mode, one frame sync word is detected, and then a first pointer (AU-4) is read which is spaced a predetermined distance from the sync word and addresses a cell-structured data area (VC4). Then the headers of the ATM cells in the data area, which are addressed via the pointer, are decoded, and if x successive correct cell headers are decoded, a transition to the sync state takes place. If data structures of an SDH system or a purely cell-structured transmission of ATM cells have to be identified, an incoming bit sequence is checked for a predetermined frame sync word (SDH frame) and then for code words representing regularly inserted cell headers, and a change to either a frame sync mode or a cell sync mode takes place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.