Low-loss semiconductor device and backside etching method for manufacturing same
US5252842A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1991 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Jul 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/875
Abstract
A semiconductor device has material removed from the back of the substrate and a manufacturing process is provided for manufacturing these devices. In the exemplary embodiment, a GaAs FET chip is formed by a process including the step of etching the GaAs substrate from the back of the chip in a defined removal region to reduce the dielectric constant in the region of the source-to-drain path. A buffer layer of differing material provided between the active layers and the substrate prevents etching of the active layers during the removal process. To allow simplified etching patterns, the source-to-drain path may be laid out on the surface of the chip in a variety of patterns, including "packed" patterns concentrating a large path area in a small surface area of the chip. Optionally, this buffer layer may also be etched away in a further processing step. An insulating layer of material may be added to the back side of the chip in the etched region to increase structural strength, and a pressure relief ventilation path may be provided connecting the removal region to the outside at an edge or at the surface of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.