Trench DRAM cell with vertical transistor
US5252845A · kind A · utility
53Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 1992 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | May 5, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
The DRAM cell of the invention comprises a structure wherein a deep trench is formed on a silicon wafer, a stacked trench capacitor is formed around a silicon pillar associated with the trench, and a vertical transfer transistor is formed on top of the silicon pillar after the formation of the stacked trench capacitor. The transfer transistor is connected to the storage capacitor through a selectively doped n.sup.+ diffused layer, and isolation between DRAM cells is formed by the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.