Digital multiplier
US5253194A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1992 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Apr 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/53
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decode circuit decodes digital signals X1 and X0 as multiplicand to output decoded signals A0-A3. One of these decoded signals A3-A0 is set to be logic 1 in accordance with a value of a multiplicand. A logical operation circuit includes a plurality of operation circuits. Each logical operation circuit performs an independent operation for obtaining a logical value of each bit of the digital signal which is a multiplication result, based on the decoded signals A0-A3 and the digital signals R1 and R0 as a multiplier. Therefore, a result of an operation of a certain bit does not affect results of operations of other bits, so that the logical operation of each bit can be conducted without waiting termination of the logical operations of other bits, which enables high-speed multiplications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.