High speed multiplier
US5253195A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1993 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Feb 4, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed digital multiplier utilizes a variation in known shift-and-add algorithms. Each cycle, a single digit of the multiplier and the entire multiplicand are processed to form a "partial product" that is added to the result of the next cycle. The end result is a two part product, the high order product being generated by a carry-propagate adder, and the low order product being generated by a "spill adder" that produces one digit each cycle. Inputs of a carry-propagate adder are fed directly from outputs of a carry-save adder rather than running sum and carry registers. With a multiplier digit of 16-bits, a fixed point halfword multiply requires one execution cycle, a fixed point fullword multiply requires two execution cycles, and a floating point long multiply requires four execution cycles with additional overhead if pre- or post-normalization is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.