Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip
US5253255A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1990 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Nov 2, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.