Method of combining lower order and translated upper order bits to address ROM within a range reserved for other devices
US5253350A · kind A · utility
16Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1990 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Jul 19, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to an address decoded in a preselected range, a multiplexer combines translated high order address bits with CPU-generated low order address bits to access random access memory, especially reserved range random access memory. Otherwise, the multiplexer merely combines CPU-generated low order bits with CPU-generated high order address bits to access RAM. An expanded memory specification memory map drives the translator to generate the translated high order address bits. This generates the address for reserved range RAM. RAM contents, normal and reserved range, are available for processing by the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.