Method and apparatus for pipelining cache accesses using anticipatory initiation of cache read
US5253352A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1989 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Nov 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed memory component, such as a cache RAM (random access memory), has a bidirectional data line and a control line (CDRAMOE) which, when respectively set to first and second electrical states, causes the memory component to respectively output data onto and accept data from the bidirectional data line. An arrangement is provided to initiate transfers of data to and from the memory component on the bidirectional data line and to produce at a first point in time a valid indication signal (W/R) indicating that one of a data read and a data write is being initiated. A method and apparatus for controlling the memory component involve the control line being set to the second electrical state at a second point in time prior to the first point in time, and the control line being maintained in the second electrical state from the second point in time to the first point in time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.